SMCube HDL for Lattice allows you to generate Verilog Lattice Diamond MSB components starting from a graphical representation of a state machine.
In other words, SMCube HDL allows the design of Verilog HDL Synchronous Finite State Machines (FSM) in a simple way, moreover simplifying the integration with the Lattice Diamond tools.
For more information on the various version of SMCube, please refer to the SMCube product page
With SMCube HDL you can:
- Edit the graphical representation of a state machine;
- Simulate the state machine graphically;
- Generate a MSB component directory structure ready to be integrated in your Lattice MSB platform;
- Finite state machine specification using graphical notation inspired to UML.
- Internal data model including: Input/output 32-bit registers visible on the Wishbone bus as a slave peripheral. Input and output pins that are exported outside the component; Local registers for storing internal states.
- 0-time graphical simulation of the state machine from an editable input sequence.
- Generation of a complete Diamond MSB Component composed by: a Verilog implementation of the state machine, a Verilog Wishbone wrapper, .H files for accessing the component registers in C language, and all accompanying files needed to create a MSB Component.
- Input filtering: automatic generation of input filtering methods (nothing, registrer).
- External logic support: an external module can be configured to interact with the state machine. The external module can read the internal data model and can supply additional input to influence the state machine evolution.
- IRQ line to generate interrupts on demand, synchronous and asynchronous reset and clock enable support.
- The generator is able to generate Verilog HDL code as well as a .h file for the component registers. VHDL code generation is not yet supported.
- Various examples are available, including FSMs for implementing peripherals like Encoder, PWM, Timer, external logic.